ARM



The ARM University Program, ARM Architecture Fundamentals 40min / sehr gutes engl. Video

ARM ArchitectureReference Manual





ARM Architecture

RISC

features:

• a large uniform register file

• a load/store architecture, where data-processing operations only operate on register contents, not

directly on memory contents

simple addressing modes, with all load/store addresses being determined from register contents and instruction fields only

uniform and fixed-length instruction fields, to simplify instruction decode.



In addition, the ARM architecture provides:

control over both the Arithmetic Logic Unit (ALU) and shifter in most data-processing instructions to maximize the use of an ALU and a shifter

auto-increment and auto-decrement addressing modes to optimize program loops

Load and Store Multiple instructions to maximize data throughput

conditional execution of almost all instructions to maximize execution throughput.

Processor modes



ARM registers

Exceptions

ARM supports seven types of exception, and a privileged processing mode for each type. The seven types of exception are:

The exception process

When an exception occurs, the ARM processor halts execution in a defined manner and begins execution at one of a number of fixed addresses in memory, known as the exception vectors.

An operating system installs a handler on every exception at initialization. Privileged operating system tasks are normally run in System mode to allow exceptions to occur within the operating system without state loss.

Status registers

All processor state other than the general-purpose register contents is held in status registers.

Instruction set

Arm Instructions vs. Thumb instruction set

The ARM instruction set can be divided into six broad classes of instruction:

Almost all ARM instructions contain a 4-bit condition field.

Load and store instructions

addressing modes

Adressraum

Bei Adress-Überlauf entsteht der Zustand UNPRDICTABLE

Endianness

e.g. 0x3A4B5C6D



Synchronisation

The Jazelle Extension

Saturated Integer Operations

Saturated Q15 and Q31 arithmetic

Q31 number = A 32-bit signed value can be treated as having a binary point immediately after its sign bit. This is equivalent to dividing its signed integer value by 2 31 , so that it can now represent numbers from –1 to +1 – 2 –31 .